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How it works · Part 3

A wafer's three months in the fab

What happens to a blank disc of silicon between the day it enters a chip factory and the day its dies leave for packaging: twelve steps, a thousand process operations, and a cleanroom that never stops. Play the tour, or pick any step and drag the model.

Diagram: a cross-section of a chip from the silicon wafer up through transistors and metal wiring, beside the loop of fab steps that builds each layer: clean, deposit, lithography, etch, implant, polish, measure, and finally test The fab: about 90 days, 1,000+ steps, 60 to 100 mask layers Silicon wafer, 775 µm Transistors Wiring, 12 to 18 levels of copper One mask layer about a day · ×60 to 100 Clean Deposit Expose Etch Implant Polish Measure Test
A fab hall and three exhibits, not to one scale: the cross-section is a few transistors magnified a hundred thousand times. Figures are for a 3 nm or 2 nm class logic process unless a step says otherwise.
Playing the tour

    Step 1 of 12

    A thousand steps, around the clock

    A blank wafer that enters a leading-edge fab comes out finished about three months later, after well over a thousand operations on the same few kinds of machine.

    Time in the fab
    ~3 months
    Process steps
    1,000+
    Mask layers
    60 to 100
    Wafer diameter
    300 mm
    Transistors per mm²
    200 to 300 million
    Metal levels
    12 to 18
    Leading-edge fab
    $20 billion+
    Finished wafer, 3 nm class
    ~$20,000

    The words that come up

    Twelve terms from the fab floor and the equipment makers' earnings calls.

    Wafer start
    One blank wafer entering the line. Fab capacity is quoted in wafer starts per month; TSMC's biggest sites exceed 100,000.
    Cycle time
    How long a wafer takes from start to finish: around three months at the leading edge, roughly a day to a day and a half per mask layer.
    Mask layer
    One pass through lithography with one photomask. An advanced logic process has 60 to 100; 15 to 25 of them use EUV.
    FEOL / BEOL
    Front end of line, the layers that make the transistors; back end of line, the metal levels that wire them. Contacts in between are the middle of line.
    FOUP
    The sealed carrier that holds 25 wafers and rides the overhead transport between tools. Wafers see the cleanroom air only inside a tool.
    Photoresist
    The light-sensitive film that is exposed through the mask and developed into a stencil for etching or implanting.
    Plasma etch
    Removing material with ions driven straight down through the stencil, so that trenches have vertical walls. Lam Research and Tokyo Electron lead.
    ALD
    Atomic layer deposition: films grown one layer of atoms per cycle, a tenth of a nanometre at a time, even inside deep holes.
    CMP
    Chemical-mechanical planarisation: polishing the wafer flat with an abrasive slurry before each exposure, and the step that made copper wiring possible.
    Overlay
    How precisely one layer lands on the layer beneath, measured in nanometres and checked after every exposure.
    Yield
    The share of dies on a wafer that work. A new process starts low and climbs; a mature one kills fewer than one die in ten.
    Known-good die
    A die that passed wafer sort. Only these go on to packaging, where they are joined to their memory and tested again.

    Figures from TSMC, Samsung and Intel technology disclosures, IEDM and VLSI Symposium papers, the equipment makers' investor materials (ASML, Applied Materials, Lam Research, Tokyo Electron, KLA) and the trade press (SemiAnalysis, EE Times, Semiconductor Engineering). Simplified: a real process flow has thousands of distinct recipes, and every fab's is secret.

    Next in the series: How a language model works · Part 5: How 100,000 GPUs talk · Part 2: How a GPU works · Part 1: How EUV lithography prints a chip